Memory devices are commonly included as internal data storage devices in a computer. One very common type of memory is random access memory (RAM). RAM is memory into which you can both write data into memory and read data from memory. These features make RAM needed as a primary memory in a computer. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. An interruption in power would thus lose data stored in RAM.
Computers also utilize some read only memory (ROM), which is used to store data that may be read only and does not allow data to be written. One type of ROM is electrically erasable programmable read only memory (EEPROM). This memory may be electronically erased. EEPROM comprises a large number of floating gates on which charge is stored to store data. Charge may be removed or added to these floating gates by specialized operations (i.e., erase or programming instructions).
One specific type of EEPROM is Flash memory, which is programmed and erased in blocks of data. A Flash memory generally includes a number of memory cells (e.g., a floating gate transistor for holding a charge) arranged in a memory array. The array groups memory cells into a block that can be programmed by charging the floating gate, or erased by changing the state of all the floating gate memory cells in the block in a single operation.
Commonly, Flash memories include registers to secure data. Protection registers are a limited size, special purpose non-volatile storage areas. Such protection registers are separate from the erase blocks noted above and are used for storage of device identifiers, security codes, erase block content date or other similar data. Once programmed, a programmer may lock the protection register by programming lock bits that, once set, may not be altered by the ultimate end user. The floating cells of the erase bits have no erase capability that can be accessed by the end user (factory-erasable), and once locked maintain their data in a fixed state.
Many protection registers are 128 bits, sufficiently long to allow the protection register to be used for storage of device identifiers, security codes or other data associated with the Flash memory device or the data contents of the erase blocks. A 128 bit protection register can be eight words divided into two 64-bit blocks, an A block and a B block. The A block is programmed by the manufacturer, and cannot be subsequently modified by the user. The user can program the B Block. The user can lock the B Block, preventing the data in this block from being subsequently modified.
In one product, an A Block is accessed at address 81-84h and Block B at address 85-88h. The A Block and B Block are accessed in the product ID mode. The status of the B Block can be determined at the address 80h. For the B Block, the lock status is stored in a fuse in the fuse array. Each fuse consists of three memory cells that are tied together. The use of three cells tied together is to enhance readability, since read failure/error cannot be tolerated because the lock status date relates to device configuration. Since the fuse is external to the protection register array, the fuse is read immediately upon device activation. All fuses are read and latched at power up. The lock status information is stored on its own dedicated lines. Thus when the command sequence for B Block program is entered, the command user interface (CUI) already knows the lock status of B Block and can start the program or not start the program algorithm as specified by the protection register information instructions.
However as Flash memory becomes ever larger and more complex, there is a need for additional protection registers. However, the inclusion of the additional protection registers introduce difficulties in determining the lock status of the protection registers in a group of protection registers—a protection register array.
Therefore, one advantage of the present invention is to provide a method for determining a lock status of the protection resisters in a protection register array in which the lock status may be determined even if the ordinary methods of determining lock status (as fuses) of the protection register are not practicable given the number of associated cells that would need to be modified exceed the system capability in certain circumstances.